//***************************
module RAM
(
    input clk,
    
    input [7:0] wr_data, 
    input [7:0] wr_addr,
    input wr_en,
    
    output reg [15:0] rd_inst,
    input [7:0] rd_inst_addr,
    
    output reg [7:0] rd_data,
    input [7:0] rd_data_addr    
    
);

reg [7:0] ram [0:255];

initial $readmemb("addArray.data", ram);
initial $monitor("time %4d: mem[128] %3d", $time, ram[128]);

always @(rd_inst_addr)
begin
    rd_inst[7:0] = ram[rd_inst_addr];
    rd_inst[15:8] = ram[rd_inst_addr+1];
end

always @(rd_data_addr) begin
    rd_data[7:0] = ram[rd_data_addr];    
end



always @(posedge clk)
begin
    if(wr_en) begin
        ram[wr_addr]<=wr_data;        
    end
end

endmodule